Hardware designers and verification engineers have embraced the use of assertions. They are a way to formally specify a design's intended behavior, which must hold true during the course of a design ...

There has been a lot of talk in the industry about the usefulness of assertions as part of a complete verification methodology. But there is something bigger going on here that many vendors are ...

Why is it still so hard to ensure good quality sign-off happens without leaving behind bugs in silicon? The answer, according to my colleagues at DVCon, is highly nuanced. The industry has been ...