GitHub

Calculator in VHDL for the Basys3 development board

If you want to simulate one unit of the calculator project head to the file "/msim/sim.do". Uncomment the line of the particular unit and comment all other units. In ModelSim change the directory to ...
GitHub

This Repository contains custom-defined (AUBIE) processor components as defined by the ModelSimPE VHDL([Very High Speed Integrated Circuit] Hardware Description Language ...

The opcode for this architecture is always found in the high order 8 bits of an instruction word (bits 31-24). Instructions can be variable length (either one dlx_word long or two words long). In ...
IEEE

ModelSim/Simulink co-simulation of sensorless PMSM speed control system with EKF estimator and adaptive fuzzy controller

Abstract: Based on the extended Kalman filter (EKF) estimator and adaptive fuzzy controller (AFC), the design of a sensorless speed control IP (Intellectual Property) for PMSM (Permanent Magnet ...
IEEE

Efficient VHDL implementation of symbol synchronization for software radio based on FPGA

Abstract: The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. One of the main sections of ...