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IEEE

Transistor sizing and gate sizing using geometric programming considering delay minimization

Abstract: A comparison between gate sizing and transistor sizing to analyze the trade-off between execution time and minimum delay achieved is presented in this work. The transistor and gate sizing ...
IEEE

Self-Clamping Programming in Narrow-Bridge Floating Gate Cells for Multi-Level Logic Non-Volatile Memory Applications

Abstract: A new self-converging programming characteristic in a single-poly floating-gate memory cell with full-compatibility to a CMOS logic technology is observed and studied. A uniquely design cell ...