IEEE

Hybrid Hardening Approach for a Fault-Tolerant RISC-V System-On-Chip

Abstract: The New Space era has driven a wide array of applications in novel space missions with an increasing demand for processors with high computational capabilities while simultaneously ...
IEEE

Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System

Abstract: The open-source and customizable features of the RISC-V Instruction Set Architecture (ISA) have facilitated its rapid adoption since its publication in 2011. The availability of numerous ...
GitHub

CoVE (RISC-V Confidential VM Extension)

The CoVE APIs are designed to be implementation and architecture agnostic, allowing for different deployment models while retaining common host and guest kernel code. Two examples are shown in Figure ...