Phase-Locked Loop Tutorial PLL Basics

A Sub-0.9-ps Static Phase Offset 500 MHz Delay-Locked Loop With a Large Gain Phase Detector

Abstract: This article presents an analog delay-locked loop (DLL) designed for high-precision measurement applications, featuring low static phase offset (SPO) and fast locking speed, such as ...

IEEE

A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector

Abstract: An integer-N digital-sampling phase-locked loop (PLL) based on a noise-shaping SAR (NS-SAR) analog-to-digital converter (ADC) breaks the quantization noise limitation of prior ADC-based ...

Some results have been hidden because they may be inaccessible to you

Show inaccessible results

A Sub-0.9-ps Static Phase Offset 500 MHz Delay-Locked Loop With a Large Gain Phase Detector

A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector

Trending now