IEEE

Spike-RISC: Algorithm/ISA Co-Optimization for Efficient SNNs on RISC-V

Abstract: Artificial intelligence has proven its benefits in many domains. Yet, traditional deep learning models are still too energy and compute-intensive for resource-constrained edge environments.
IEEE

Leveraging RISC-V for HW/SW Codesign of Flexible and Efficient TinyML SoCs

Abstract: Editor’s notes: This keynote article presents a comprehensive and impactful contribution to energy-efficient TinyML through the design of domain-specific RISC-V instruction set architecture ...
Digi Times

MIPS accelerates S8200 RISC-V NPU timeline

MIPS has accelerated the development timeline of its S8200 neural processing unit, a RISC-V–based NPU designed for real-time, low-latency edge AI, as the company continues to advance its strategy ...
Digi Times

MIPS expands RISC-V processor platform with ARC IP integration

MIPS is repositioning itself within the RISC-V ecosystem following the integration of the ARC Processor IP business acquired from Synopsys, moving beyond a CPU-centric model toward a broader processor ...