IEEE

HSP-V: Hypervisor-Less Static Partitioning for RISC-V COTS Platforms

Abstract: Virtualization technology has played a pivotal role in consolidating Mixed-Criticality Systems (MCS) onto a single computing platform. However, not all RISC-V processors present in ...
IEEE

Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System

Abstract: The open-source and customizable features of the RISC-V Instruction Set Architecture (ISA) have facilitated its rapid adoption since its publication in 2011. The availability of numerous ...
Digi Times

MIPS accelerates S8200 RISC-V NPU timeline

MIPS has accelerated the development timeline of its S8200 neural processing unit, a RISC-V–based NPU designed for real-time, low-latency edge AI, as the company continues to advance its strategy ...
Digi Times

MIPS expands RISC-V processor platform with ARC IP integration

MIPS is repositioning itself within the RISC-V ecosystem following the integration of the ARC Processor IP business acquired from Synopsys, moving beyond a CPU-centric model toward a broader processor ...