EDN

Eddy current in focus: A rapid revisit

From DIY levitation tricks to clever braking systems, these swirling paths of electrons keep finding new ways to surprise and inspire.
IEEE

AIL-DNN: Modeling of IC Interconnect Parasitic Capacitances Based on Adaptive Incremental Learning

Abstract: The accurate extraction of interconnect parasitic capacitance is a critical issue for designing VLSI circuits. To improve the efficiency of parasitic capacitance extraction, we present in ...
IEEE

Optimized Partitioning of VLSI Circuits with Particle Swarm Optimization for Improved Performance

Abstract: In the context of interconnection cost, delay, and sleep mode power efficiency, optimized partitioning of VLSI circuits becomes important. This research work proposes a Particle Swarm ...
Hackaday

LiPo charger

Nothing brings joy to a hacker’s heart like taking a cheap gizmo and making it useful. Over at Hackaday.io [AndyHull] popped open some cheap LiPo battery power packs to see if he could power a Canon ...
GitHub

Circuit-level implementation and optimization of a 16:1 lookup table (LUT) in 45 nm CMOS and pass-transistor logic. Includes schematic design, Cadence simulations, and Elmore ...

Circuit-level implementation and optimization of a 16:1 lookup table (LUT) in 45 nm CMOS and pass-transistor logic. Includes schematic design, Cadence simulations, and Elmore delay analysis.