IEEE

Performance Analysis of a New Low Power BIST Technique in VLSI Circuit by Reducing the Input Vectors

Abstract: VLSI circuit testing is complex and costs over 30% of the total IC design. The built-in self-testing technique is popular for its extensive fault coverage and efficiency. BIST refers to a ...
IEEE

Energy-Efficient Sequential Circuit Design Using Optimized Clock-Gated Johnson Counter for Low-Power VLSI Applications

Abstract: The modern design of VLSI has primarily focused on the minimization of power dissipation. The dimensions of chips are decreasing, and reliability enhancement through advancements in ...